MOSFET transistor modeling including parasitic leakage and drain resistance

Abstract

The aim of the work is to develop and analyze a method for including parasitic source (R_S) and drain (R_D) resistances in the basic SPICE Level 1 MOSFET model. Relevance: even in the simple quadratic MOSFET model (SPICE level 1), ignoring parasitic resistances can lead to significant simulation errors, especially at high currents. This paper provides a literature review of approaches to account for R_S and R_D in compact MOSFET models: from the classic Shichman–Hodges model (SPICE Level 1) to modern works on the extraction of resistances and modeling their impact. Theoretical background describes a modification of the Level 1 model by introducing effective voltages V^eff_GS and V^eff_DS that account for voltage drops across R_S and R_D, and analytical equations for the drain current I_D in linear and saturation regions with these resistances. Methodology includes a numerical iterative algorithm implemented in Python/PySpice which solves the implicit equation I_D(V^eff_GS, V^eff_DS). Results show reduction of current and a shift in saturation point when adding parasitic resistances: for a typical NMOS at V_GS=5 V, introducing R_S=R_D=50 Ω reduces I_D by ≈16% and increases the saturation voltage by ≈ 0.3 V. Output characteristics graphs and tables of relative current deviation are presented. The novelty lies in the proposed simple iterative procedure to include R_S, R_D in the SPICE Level 1 model without resorting to more complex models, and the practical value is the applicability of this approach for educational modeling and quick evaluation of parasitic effects on MOSFET behavior. Conclusions: accounting for R_S, R_D significantly improves the accuracy of Level 1 modeling, bringing results closer to real devices with minimal computational complexity, which is useful for engineering practice and further research.